1. Field of the Invention
The present invention relates to a semiconductor device having a nonvolatile semiconductor memory element and a method of manufacturing the same and, more particularly, to a semiconductor device which improves the floating gate electrode structure of a nonvolatile semiconductor memory element and a method of manufacturing the same.
2. Description of the Related Art
A nonvolatile semiconductor memory element having a two-layered gate structure is formed by stacking a floating gate electrode and control gate electrode on a semiconductor substrate. Of the two gate electrodes, the floating gate electrode is used as a charge storage layer. The floating gate electrode is generally made of polysilicon.
However, the nonvolatile semiconductor memory element of this type has the following problem. The shape of finished polysilicon crystal grain of a floating gate electrode changes between memory elements even when they are arrayed on a single chip. When the shape of finished polysilicon crystal grain changes between memory elements, the memory characteristic such as the threshold value after write/erase operation varies between elements.
This problem will be described in detail. In manufacturing a nonvolatile semiconductor memory element having a two-layered gate structure, polysilicon for a prospective charge storage layer is deposited by CVD and then processed into an electrode pattern by RIE. At this time, the polysilicon pattern is rectangular. However, the silicon crystal grain grows in a high-temperature process such as thermal oxidation for forming an electrode sidewall oxide film. For this reason, the floating gate electrode has a final finished shape different from the rectangular shape immediately after the process. In addition, the finished shape changes between elements.
When the final finished shape of the floating gate electrode varies between elements, the electric capacitance between the floating gate electrode and the silicon substrate or that between the floating gate electrode and the control gate electrode varies between the elements. For this reason, the memory characteristic such as the threshold value after write/erase operation varies between the elements. The necessity of an excess operation time margin impedes high-speed operation. Additionally, the wide threshold value distribution hinders realizing a multilevel memory. If the variation in shape is large, the memory device causes operation errors.
Even when the silicon layer serving as the floating gate electrode is formed not in a polycrystalline state but in an amorphous state, the above problem is hard to solve. This is because the silicon layer always changes to a polycrystal in the subsequent high-temperature process.
As a prior art related to the present invention, a semiconductor device using a floating gate electrode including a layer doped with nitrogen has been proposed (Jpn. Pat. Appln. KOKAI Publication No. 9-64209). Also, a method of forming a silicon oxide film on the sidewall of a floating gate electrode by using radical oxygen has been proposed (Jpn. Pat. Appln. KOKAI Publication No. 2001-15753). A trench isolation technique using silazane polymer has also been proposed (Japanese Patent No. 3178412) (Jpn. Pat. Appln. KOKAI Publication No. 2001-319927). However, in any of the above prior arts, it is difficult to eliminate the variation in finished shape of the floating gate electrode formed from polysilicon.